This invention relates to a production method for a silicon epitaxial wafer and, more particularly, to a production method for a silicon epitaxial wafer having an internal gettering capability at a level equal to that of a Czochralski (hereinafter abbreviated as CZ) silicon mirror-finished wafer.
Heretofore, as a semiconductor wafer on which a semiconductor device such as IC, LSI or the like is fabricated, a CZ silicon mirror-finished wafer has generally been used, which is obtained by a procedure in which a wafer is cut from a silicon single crystal which has been grown by being pulled from a silicon melt by means of a CZ method and the wafer is then subjected to mirror polishing on its front surface. The silicon single crystal grown by the CZ method is supersaturated with interstitial oxygen and the interstitial oxygen is precipitated in the form of silicon oxide as the silicon single crystal is cooled down to room temperature after solidification subsequent to a crystal pulling process and due to the precipitation, a number of oxide precipitate nuclei are formed. When an IC or the like is fabricated using a CZ silicon mirror-finished wafer obtained from a silicon single crystal in which a number of the oxide precipitate nuclei are formed, the oxide precipitate nuclei grow to progress oxygen precipitation with the result that a number of microdefects induced by the oxide precipitate nuclei generate in the bulk of the wafer in a heat treatment of the device fabrication process.
A microdefect induced by an oxide precipitate nucleus preferably works as a gettering site at which heavy metal impurities and the like are captured due to the so-called internal gettering (hereinafter abbreviated as IG) effect when the microdefect exists in the interior region (bulk region). It has known, however, that if microdefects exist in the active region in the vicinity of a wafer surface where semiconductor devices are fabricated, it becomes a factor detrimental to operation of the devices which in turn entails degradation in device characteristics and exerts an adverse influence directly on the device yield.
In recent years, a demand for a silicon epitaxial wafer has been increased, which is produced by depositing silicon single crystal on a CZ silicon mirror-finished wafer in vapor phase growth (epitaxial growth), as substitution for a CZ silicon mirror-finished wafer, in order to make an active region in the vicinity of a wafer surface where semiconductor devices are fabricated defect free.
There has, however, been a problem that a silicon epitaxial wafer has a low IG capability compared with a CZ silicon mirror-finished wafer. In other words, in the case of the CZ silicon mirror-finished wafer, since a number of oxide precipitate nuclei are formed in a CZ silicon single crystal while the crystal is cooled down to room temperature after solidification in a crystal pulling process, the oxygen precipitation further progresses in a semiconductor device fabrication process through growth of the precipitate nuclei, whereas, in the case of the silicon epitaxial wafer, since an epitaxial growth process is effected at a temperature as high as the order in the range of 1100 to 1150.degree. C., oxide precipitate nuclei formed in the silicon single crystal pulling process are transited to a solution state during the epitaxial growth process, which suppresses oxygen from precipitation in the semiconductor fabrication process compared with the case of the CZ mirror-finished wafer. Hence, a silicon epitaxial wafer has the IG capability at a low level compared with a CZ silicon mirror-finished wafer.
In order to solve this problem, external gettering (hereinafter abbreviated as EG) methods have heretofore been employed, in which gettering sites are formed on the rear surface of a silicon epitaxial wafer. For example, as the EG methods, there are named: a sandblast (hereinafter abbreviated as SB) method in which defects are externally formed on the rear surface of a wafer by intention, a PBS method in which a polysilicon film is deposited on the rear surface of a wafer and the like.
In such conventional methods, a distance between a active region where semiconductor devices are fabricated (on the front surface) and a gettering site (on the rear surface) is long, which problematically causes time for impurities to be captured to be longer. Such circumstances come to be more conspicuous when a semiconductor device fabrication process is performed at a lower temperature, since a time required for an impurity to diffuse up to the rear surface of a wafer is longer. Therefore, an IG method is desirably selected to be in use, in which method a distance between an active region (on the front surface) where semiconductor devices are fabricated and a gettering site (in the bulk) is short.